////////////////////////////////////////////////////////////////////////////////
/// @file     reg_usb.h
/// @author   AE TEAM
/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
///           MM32 FIRMWARE LIBRARY.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////

// Define to prevent recursive inclusion

#ifndef __REG_USB_H
#define __REG_USB_H

// Files includes
#include <core_cm0.h>


#ifdef __cplusplus
extern "C" {
#endif

#if defined(__CC_ARM)
#pragma anon_unions
#elif defined(__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined(__GNUC__)
// anonymous unions are enabled by default
#else
#warning Not supported compiler type
#endif

////////////////////////////////////////////////////////////////////////////////
/// @brief USB Base Address Definition
////////////////////////////////////////////////////////////////////////////////
#define USB_BASE                        (AHB2PERIPH_BASE + 0x0000)              ///< Base Address: 0x50000000

////////////////////////////////////////////////////////////////////////////////
/// @brief USB Register Structure Definition
////////////////////////////////////////////////////////////////////////////////
typedef struct {
    __IO uint32_t RESERVED0x00[32];                                                  ///< Reserved                                       offset: 0x00~0x7C
    __IO uint32_t INTSTAT;                                                           ///< Interrupt Status Register                      offset: 0x80
    __IO uint32_t INTENB;                                                            ///< Interrupt Enable Register                      offset: 0x84
    __IO uint32_t ERRSTAT;                                                           ///< Error Interrupt Status Register                offset: 0x88
    __IO uint32_t ERRENB;                                                            ///< Error Interrupt Enable Register                offset: 0x8C
    __IO uint32_t STAT;                                                              ///< Status Register                                offset: 0x90
    __IO uint32_t CTL;                                                               ///< Control Register                               offset: 0x94
    __IO uint32_t ADDR;                                                              ///< Address Register                               offset: 0x98
    __IO uint32_t BDTPAGE1;                                                          ///< BDT Page Register 1                            offset: 0x9C
    __IO uint32_t FRMNUML;                                                           ///< Frame Number Register                          offset: 0xA0
    __IO uint32_t FRMNUMH;                                                           ///< Frame Number Register                          offset: 0xA4
    __IO uint32_t RESERVED0xA8[2];                                                   ///< Reserved                                       offset: 0xA8~0xAC
    __IO uint32_t BDTPAGE2;                                                          ///< BDT Page Register 2                            offset: 0xB0
    __IO uint32_t BDTPAGE3;                                                          ///< BDT Page Register 3                            offset: 0xB4
    __IO uint32_t RESERVED0xB8[2];                                                   ///< Reserved                                       offset: 0xB8~0xBC
    __IO uint32_t EPCTL0;                                                            ///< Endpoint Control Register 0                    offset: 0xC0
    __IO uint32_t EPCTL1;                                                            ///< Endpoint Control Register 1                    offset: 0xC4
    __IO uint32_t EPCTL2;                                                            ///< Endpoint Control Register 2                    offset: 0xC8
    __IO uint32_t EPCTL3;                                                            ///< Endpoint Control Register 3                    offset: 0xCC
    __IO uint32_t EPCTL4;                                                            ///< Endpoint Control Register 4                    offset: 0xD0
    __IO uint32_t EPCTL5;                                                            ///< Endpoint Control Register 5                    offset: 0xD4
    __IO uint32_t EPCTL6;                                                            ///< Endpoint Control Register 6                    offset: 0xD8
    __IO uint32_t EPCTL7;                                                            ///< Endpoint Control Register 7                    offset: 0xDC
    __IO uint32_t RESERVED0xE0[8];                                                   ///< Reserved                                       offset: 0xE0~0xFC
    __IO uint32_t CTRL;                                                              ///< USB Control register                           offset: 0x100
} USB_TypeDef;

////////////////////////////////////////////////////////////////////////////////
/// @brief USBD type pointer Definition
////////////////////////////////////////////////////////////////////////////////
#define USB                             ((USB_TypeDef*) USB_BASE )

////////////////////////////////////////////////////////////////////////////////
/// @brief USB_INTSTAT Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define USB_INTSTAT_USB_RST_Pos         (0)
#define USB_INTSTAT_USB_RST             (0x01U << USB_INTSTAT_USB_RST_Pos)      ///< When USB_FS decodes the valid USB reset, the bit is set
#define USB_INTSTAT_ERROR_Pos           (1)
#define USB_INTSTAT_ERROR               (0x01U << USB_INTSTAT_ERROR_Pos)        ///< In case of any error condition of ERRSTAT register, the bit is set
#define USB_INTSTAT_SOF_TOK_Pos         (2)
#define USB_INTSTAT_SOF_TOK             (0x01U << USB_INTSTAT_SOF_TOK_Pos)      ///< If USB_FS receives SOF token, the bit is set.
#define USB_INTSTAT_TOK_DNE_POS         (3)
#define USB_INTSTAT_TOK_DNE             (0x01U << USB_INTSTAT_TOK_DNE_Pos)      ///< After the token processing, the bit is set.
#define USB_INTSTAT_SLEEP_Pos           (4)
#define USB_INTSTAT_SLEEP               (0x01U << USB_INTSTAT_SLEEP_Pos)        ///< When the USB_FS detects 3ms idle in the USB bus signal, the bit is set as ‘1’.
#define USB_INTSTAT_RESUME_Pos          (5)
#define USB_INTSTAT_RESUME              (0x01U << USB_INTSTAT_RESUME_Pos)       ///< This bit is used to transmit Remote Wakeup signal.

#define USB_INTSTAT_STALL_Pos           (7)
#define USB_INTSTAT_STALL               (0x01U << USB_INTSTAT_STALL_Pos)        ///< In the device mode, SIE sends the STALL handshake packet, and it’s set.

////////////////////////////////////////////////////////////////////////////////
/// @brief USB_INTENB Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define USB_INTENB_USB_RST_Pos          (0)
#define USB_INTENB_USB_RST              (0x01U << USB_INTENB_USB_RST_Pos)       ///< Set the bit as 1, and enable ERROR interrupt.
#define USB_INTENB_ERROR_Pos            (1)
#define USB_INTENB_ERROR                (0x01U << USB_INTENB_ERROR_Pos)         ///< Set the bit as 1, and enable ERROR interrupt.
#define USB_INTENB_SOF_TOK_Pos          (2)
#define USB_INTENB_SOF_TOK              (0x01U << USB_INTENB_SOF_TOK_Pos)       ///< Set the bit as 1, and enable SOF_TOK interrupt.
#define USB_INTENB_TOK_DNE_Pos          (3)
#define USB_INTENB_TOK_DNE              (0x01U << USB_INTENB_TOK_DNE_Pos)       ///< Set the bit as 1, and enable TOK_DNE interrupt.
#define USB_INTENB_SLEEP_Pos            (4)
#define USB_INTENB_SLEEP                (0x01U << USB_INTENB_SLEEP_Pos)         ///< Set the bit as 1, and enable SLEEP interrupt.
#define USB_INTENB_RESUME_Pos           (5)
#define USB_INTENB_RESUME               (0x01U << USB_INTENB_RESUME_Pos)        ///< Set the bit as 1, and enable RESUME interrupt.

#define USB_INTENB_STALL_Pos            (7)
#define USB_INTENB_STALL                (0x01U << USB_INTENB_STALL_Pos)         ///< Set the bit as 1, and enable STALL interrupt.

////////////////////////////////////////////////////////////////////////////////
/// @brief USB_ERRSTAT Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define USB_ERRSTAT_PID_ERR_Pos         (0)
#define USB_ERRSTAT_PID_ERR             (0x01U << USB_ERRSTAT_PID_ERR_Pos)      ///< PID check field failure.
#define USB_ERRSTAT_CRC5_EOF_Pos        (1)
#define USB_ERRSTAT_CRS5_EOF            (0x01U << USB_ERRSTAT_CRC5_EOF_Pos)     ///< The interrupt will detect the CRC5 error in the token data packet generated by the host.
#define USB_ERRSTAT_CRC16_Pos           (2)
#define USB_ERRSTAT_CRC16               (0x01U << USB_ERRSTAT_CRC16_Pos)        ///< CRC16 check error. If the data packet is refused because of CRC16 error, the bit is set.
#define USB_ERRSTAT_DFN8_Pos            (3)
#define USB_ERRSTAT_DFN8                (0x01U << USB_ERRSTAT_DFN8_Pos)         ///< The received data field is not 8 bits. If the data field is not the integer byte, the bit is set.
#define USB_ERRSTAT_BTO_ERR_Pos         (4)
#define USB_ERRSTAT_BTO_ERR             (0x01U << USB_ERRSTAT_BTO_ERR_Pos)      ///< In case of bus turnover timeout error, this bit is set.
#define USB_ERRSTAT_DMA_ERR_Pos         (5)
#define USB_ERRSTAT_DMA_ERR             (0x01U << USB_ERRSTAT_DMA_ERR_Pos)      ///< If USB_FS requests DMA access to read new BDT, and the bus is not given before USB_FS needs to receive or transmit data, the bit is set as ‘1’

#define USB_ERRSTAT_BTS_ERR_Pos         (7)
#define USB_ERRSTAT_BTS_ERR             (0x01U << USB_ERRSTAT_BTS_ERR_Pos)      ///< Set in case of detection of bit stuff error.

////////////////////////////////////////////////////////////////////////////////
/// @brief USB_ERRENB Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define USB_ERRENB_PID_ERR_Pos          (0)
#define USB_ERRENB_PID_ERR              (0x01U << USB_ERRENB_PID_ERR_Pos)       ///< Set the bit and enable PID_ERR interrupt.
#define USB_ERRENB_CRC5_EOF_Pos         (1)
#define USB_ERRENB_CRS5_EOF             (0x01U << USB_ERRENB_CRC5_EOF_Pos)      ///< Set the bit as 1 and enable CRC5/EOF interrupt.
#define USB_ERRENB_CRC16_Pos            (2)
#define USB_ERRENB_CRC16                (0x01U << USB_ERRENB_CRC16_Pos)         ///< Set the bit as 1 and enable CRC16 interrupt.
#define USB_ERRENB_DFN8_Pos             (3)
#define USB_ERRENB_DFN8                 (0x01U << USB_ERRENB_DFN8_Pos)          ///< Set the bit as 1 and enable DFN8 interrupt.
#define USB_ERRENB_BTO_ERR_Pos          (4)
#define USB_ERRENB_BTO_ERR              (0x01U << USB_ERRENB_BTO_ERR_Pos)       ///< Set the bit as 1 and enable BTO_ERR interrupt.
#define USB_ERRENB_DMA_ERR_Pos          (5)
#define USB_ERRENB_DMA_ERR              (0x01U << USB_ERRENB_DMA_ERR_Pos)       ///< Set the bit as 1 and enable DMA_ERR interrupt.

#define USB_ERRENB_BTS_ERR_Pos          (7)
#define USB_ERRENB_BTS_ERR              (0x01U << USB_ERRENB_BTS_ERR_Pos)       ///< Set the bit as 1 and enable BTS_ERR interrupt.

////////////////////////////////////////////////////////////////////////////////
/// @brief USB_STAT Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define USB_STAT_ODD_Pos                (2)
#define USB_STAT_ODD                    (0x01U << USB_STAT_ODD_Pos)             ///< This bit indicates that the last buffer descriptor is located in the BDT odd number group.
#define USB_STAT_TX_Pos                 (3)
#define USB_STAT_TX                     (0x01U << USB_STAT_TX_Pos)              ///< The bit indicates BDT transmission direction since the last refresh
#define USB_STAT_ENDP_Pos               (4)
#define USB_STAT_ENDP                   (0X0FU << USB_STAT_ENDP_Pos)            ///< Indicate the End Point address of the previous token

////////////////////////////////////////////////////////////////////////////////
/// @brief USB_CTL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define USB_CTL_USB_EN_Pos              (0)
#define USB_CTL_USB_EN                  (0x01U << USB_CTL_USB_EN_Pos)           ///< Set the bit as 1 and USB_FS works. Clearing it will disable USB_FS
#define USB_CTL_ODD_RST_Pos             (1)
#define USB_CTL_ODD_RST                 (0x01U << USB_CTL_ODD_RST_Pos)          ///< Set the bit and reset all BDT ODD ping/pong bit as 0, and then specify the even number BDT.
#define USB_CTL_RESUME_Pos              (2)
#define USB_CTL_RESUME                  (0x01U << USB_CTL_RESUME_Pos)           ///< Setting this bit will allow the USB-FS to execute resume signaling.

#define USB_CTL_TXDSUSPENDTOKENBUSY_Pos (5)
#define USB_CTL_TXDSUSPENDTOKENBUSY     (0x01U << USB_CTL_TXDSUSPENDTOKENBUSY_Pos)   ///< This bit informs the processor that the SIE has disable packet transmission and reception
#define USB_CTL_SE0_Pos                 (6)
#define USB_CTL_SE0                     (0x01U << USB_CTL_SE0_Pos)              ///< USB receives SE0 signal.
#define USB_CTL_JSTATE_Pos              (7)
#define USB_CTL_JSTATE                  (0x01U << USB_CTL_JSTATE_Pos)           ///< USB differential receiver receives JSTATE signal.

////////////////////////////////////////////////////////////////////////////////
/// @brief USB_ADDR Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define USB_ADDR_Pos                    (0)
#define USB_ADDR                        (0x7FU << USB_ADDR_Pos)                 ///< The USB address decoded by USB_FS in the device mode.

////////////////////////////////////////////////////////////////////////////////
/// @brief USB_BDTPAGE1 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define USB_BDTPAGE1_BDT_BA_Pos         (1)
#define USB_BDTPAGE1_BDT_BA             (0x7FU << USB_BDTPAGE1_BDT_BA_Pos)      ///< This 7 bit value provides address bits 15 through 9 of the BDT base address, which defines where the Buffer Descriptor Table resides at in system memory.

////////////////////////////////////////////////////////////////////////////////
/// @brief USB_FRMNUML Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define USB_FRMNUML_FRM_Pos             (0)
#define USB_FRMNUML_FRM                 (0xFFU << USB_FRMNUML_FRM_Pos)          ///< These bits indicate the low 8 bits of the 11 bit frame.

////////////////////////////////////////////////////////////////////////////////
/// @brief USB_FRMNUMH Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define USB_FRMNUMH_FRM_Pos             (0)
#define USB_FRMNUMH_FRM                 (0x07U << USB_FRMNUMH_FRM_Pos)          ///< These bits indicate the high 3 bits of the 11 bit frame.

////////////////////////////////////////////////////////////////////////////////
/// @brief USB_BDTPAGE2 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define USB_BDTPAGE2_BDT_BA_Pos         (0)
#define USB_BDTPAGE2_BDT_BA             (0xFFU << USB_BDTPAGE2_BDT_BA_Pos)      ///< This 8 bit value provides address bits 23 through 16 of the BDT base address, which defines where the Buffer Descriptor Table resides at in system memory.

////////////////////////////////////////////////////////////////////////////////
/// @brief USB_BDTPAGE3 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define USB_BDTPAGE3_BDT_BA_Pos         (0)
#define USB_BDTPAGE3_BDT_BA             (0xFFU << USB_BDTPAGE3_BDT_BA_Pos)      ///< This 8 bit value provides address bits 23 through 16 of the BDT base address, which defines where the Buffer Descriptor Table resides at in system memory.

////////////////////////////////////////////////////////////////////////////////
/// @brief USB_EPCTL0~7 Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define USB_EPCTL_EP_HSHK_Pos           (0)
#define USB_EPCTL_EP_HSHK               (0x01U << USB_EPCTL_EP_HSHK_Pos)
#define USB_EPCTL_EP_STALL_Pos          (1)
#define USB_EPCTL_EP_STALL              (0x01U << USB_EPCTL_EP_STALL_Pos)
#define USB_EPCTL_EP_TX_EN_Pos          (2)
#define USB_EPCTL_EP_TX_EN              (0x01U << USB_EPCTL_EP_TX_EN_Pos)
#define USB_EPCTL_EP_RX_EN_Pos          (3)
#define USB_EPCTL_EP_RX_EN              (0x01U << USB_EPCTL_EP_RX_EN_Pos)
#define USB_EPCTL_EP_CTL_DIS_Pos        (4)
#define USB_EPCTL_EP_CTL_DIS            (0x01U << USB_EPCTL_EP_CTL_DIS_Pos)

////////////////////////////////////////////////////////////////////////////////
/// @brief USB_CTRL Register Bit Definition
////////////////////////////////////////////////////////////////////////////////
#define USB_CTRL_SUSPE_Pos              (7)
#define USB_CTRL_SUSPE                  (0x01U << USB_CTRL_SUSPE_Pos)           ///< The on-chip USB PHY suspend state enable bit is used when the USB controller is in the suspend state.

/// @}

/// @}

/// @}

#ifdef __cplusplus
}
#endif

////////////////////////////////////////////////////////////////////////////////
#endif
////////////////////////////////////////////////////////////////////////////////
